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QL5022 QuickPCI Data Sheet
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33 MHz/32-bit PCI Host Capable Master Target with Embedded Programmable Logic
Device Highlights
High Performance PCI Controller
* 32-bit / 33 MHz PCI Master/Target with * * * * * * * * * *
Programmable Logic
* 387 Logic Cells * 250 MHz 16-bit counters and 275 MHz
Embedded Programmable Logic Zero-wait state PCI Master provides 132 MBps transfer rates Programmable back-end interface to optional local processor Independent PCI bus (33 MHz) and local bus (up to 160 MHz) clocks Fully Customizable PCI Configuration Space Reference design with driver code (Win 95/98/Win 2000/NT4.0) available PCI v2.2 compliant Supports Type 0 Configuration Cycles in Target mode 3.3 V, 5 V tolerant PCI signaling supports Universal PCI Adapter designs High performance PCI controller 3.3 V CMOS in 208-pin PQFP and 144-pin TQFP packages Supports unlimited/continuous burst transfers
datapaths * All back-end interface and glue-logic can be implemented on chip * Three 32-bit bus interfaces between the PCI Controller and the Programmable Logic
PCI Bus 33 MHz/32 bits (data and address)
Master Controller
High Speed Data Path
PCI Controller
Target Controller
32 bit Interface Programmable Logic
Config space High Speed Logic Cells DMA Controller
119/63 User I/O PCI Bus
Figure 1: QL5022 Block Diagram
Extendable PCI Functionality
* Support for Configuration Space from 0 x 40 to * * * *
Architecture Overview
The QL5022 device in the QuickLogic(R) QuickPCITM ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with 25,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps). The programmable logic portion of the device contains 387 QuickLogic logic cells. The QL5022 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. The QL5022 device features 3.3 V operation with multi-volt compatible I/Os. Thus, it can easily operate in 3 V systems and is fully compatible with 3.3 V, 5 V, or Universal PCI card development.
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0 x 3FF Multi-Function, Expanded Capabilities, and Expansion ROM capable Power Management, Compact PCI, Hot-Swap/Hot-Plug compatible PCI v2.2 Power Management Specification compatible PCI v2.2 Vital Product Data (VPD) configuration support
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QL5022 QuickPCI Data Sheet Rev. C
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Master/Target Controller. It is capable of infinite length Master Write and Read transactions at zero wait state (132 MBps). The Master will never insert wait states during transfers, so data should be supplied or received by the logic in the programmable region of the device. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. A DMA Controller reference design is available. The Target interface offers full PCI Configuration Space and flexible target addressing. Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and optional PCI 2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided. The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. References to DMA controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be minimized.
Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of PCI commands supported by the QL5022. QuickLogic provides a reference Address Register/Counter and Command Decode block.
DMA Master/Target Control
The customizable DMA controller included with the QuickWorks(R) design software contains the following features:
* Supports DMA transfer from PCI to external * Configurable DMA burst size for PCI * DMA Registers may be mapped to any area of Target Memory Space * Read Address (32-bit register) * Read Length (16-bit register) * Control and Status (32-bit register, includes 2 bit Burst Length) * DMA Registers are available to the local design or the PCI bus * Programmable Interrupt Control to signal end of transfer or other event
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QL5022 QuickPCI Data Sheet Rev. C
Internal PCI Interface
Figure 2 shows the interface symbol you will use in your schematic design to attach the local interface programmable logic design to the PCI core. If you were designing with a top-level Verilog(R) or VHDL file, then you would use a structural instantiation of this PCI32 block, instead of a graphical symbol.
Figure 2: PCI Interface Symbol
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QL5022 QuickPCI Data Sheet Rev. C
PCI Master Interface
Table 1 lists the internal signals used to interface with the PCI controller in the QL5022 along with a description of each signal. The direction of the signal indicates if it is an input provided by the local interface (I) or an output provided by the PCI controller (O). Signals that end with the character `N' should be considered active-low (for example, Mst_IRDYN).
Table 1: PCI Controller Signals Signal I/O Description Address for master DMA Writes. This address must be treated as valid from the beginning of a DMA burst write until the DMA write operation is complete. It must be incremented by four each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported. Address for master DMA Reads. This address must be treated as valid from the beginning of a DMA burst read until the DMA read operation is complete. It must be incremented by four each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported. DMA state machine in Write mode. This must be asserted at the beginning of a Master Transfer, and must be held until the Master Transfer completed (Mst_WrBurst_Done). DMA state machine in Read mode. This must be asserted at the beginning of a Master Transfer, and must be held until the Master Transfer completed (Mst_RdBurst_Done). Request use of the PCI bus. This signal should be held from when the DMA controller is ready to provide the first data, until the transfer is complete (Mst_WrBurst Done or Mst_RdBurst_Done). This signals to the PCI core that one data transfer remains in the burst. This signal must be asserted when only one DWORD remains to be transferred on the PCI bus. Two or less data transfers remain in the burst. This signal must be asserted when two or less DWORDs remain to be transferred on the PCI bus. Data for master DMA writes (to PCI bus). Data valid on Mst_WrData[31:0]. Data receive acknowledge for Mst_WrData[31:0]. This serves as a POP control for a FIFO which provides data to the PCI core. Master Write pipeline is empty, which indicates that the Write burst transaction is completed.
Mst_WrAd[31:0]
I
Mst_RdAd[31:0]
I
Mst_WrMode
I
Mst_RdMode
I
Mst_Burst_Req
I
Mst_One_Read
I
Mst_Two_Reads Mst_WrData[31:0] Mst_WrData_Valid Mst_WrData_Rdy Mst_WrBurst_Done Mst_RdData[31:0] Mst_RdData_Valid Mst_RdBurst_Done
I I I O O
O Data for master DMA reads (from PCI bus). O O Data valid on Mst_RdData[31:0]. This serves as a PUSH control for a FIFO that receives data from the PCI core. Master read pipeline is empty, which indicates that Read burst transaction is completed.
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QL5022 QuickPCI Data Sheet Rev. C Table 1: PCI Controller Signals (Continued) Signal I/O Description PCI command to be used for the master transaction. This signal must remain unchanged throughout the period when Mst_Burst_Req is active. PCI commands considered as Reads include Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as Writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate. Users should make sure that only valid PCI commands are supplied. Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch). For full PCI compliance, this port should be always set to 1. Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read operations.
PCI_Cmd[3:0]
I
Mst_LatCntEn
I
Mst_Xfer_D1 Mst_Last_Cycle Mst_REQN Mst_IRDYN Mst_Tabort_Det Mst_TTO_Det
O
O Active during the last data transfer of a PCI master transaction. O O O O The PCI REQN signal generated by this device as PCI master. Not usually used in the back-end design. The PCI IRDYN signal generated by this device as PCI master. Not usually used in the back-end design. Target abort detected during master transaction. This is normally an error condition to be handled in the DMA controller. Target timeout detected (no response from target). This is normally an error condition to be handled in the DMA controller.
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QL5022 QuickPCI Data Sheet Rev. C
PCI Target Interface
Table 2: PCI Target Interface Signals Signal I/O Description
Usr_Addr_WrData [31:0]
Target address and data from target Writes. During all target accesses, the address will be presented on Usr_Addr_WrData[31:0] and simultaneously, O Usr_Adr_Valid will be active. During target Write transactions, this port will present write data to the PCI configuration space or user logic. PCI command and byte enables. During target accesses, the PCI command will be presented on Usr_CBE[3:0] and simultaneously, O Usr_Adr_Valid will be active. During target Read or Write transactions, this port will present active-low byte-enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to O determine if this address belongs to the device's memory space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal will be low, indicating that data (not an address) is present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer was completed. During burst target accesses, the target address O is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented by four for subsequent data transfers. This signal will be active for the duration of a target Write transaction, and O may be used by back-end logic to turn on output-enables for transmitting the data off-chip. Active when a user Read command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI Read commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. Active when a user Write command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI Write commands, such as Memory Write or I/O Write. The address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h).
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_WrReq
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write Cfg_Write Cfg_RdData[31:0]
O Write enable for data on Usr_Addr_WrData[31:0] during PCI writes. O I Write enable for data on Usr_Addr_WrData[31:0] during PCI configuration Write transactions. Data from the PCI configuration registers, required to be presented during PCI configuration reads.
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QL5022 QuickPCI Data Sheet Rev. C Table 2: PCI Target Interface Signals (Continued) Signal Usr_RdData[31:0] Cfg_CmdReg8 I Cfg_CmdReg6 Cfg_LatCnt[7:0] I I/O I Description Data from the back-end user logic (and/or DMA configuration registers), required to be presented during PCI reads. Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h). 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Used when a target Read operation should return the value set on the Mst_RdAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Used when a target Read operation should return the value set on the Mst_WrAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h).
Usr_MstRdAd_Sel
I
Usr_MstWrAd_Sel
I
Cfg_PERR_Det
O
Cfg_SERR_Sig
System error asserted on the PCI bus. When this signal is active, the O Signalled System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Data parity error detected on the PCI bus by the master. When this O signal is active, bit 8 of the Status Register must be set in the PCI configuration space (offset 04h). O Copy of the TRDYN signal as driven by the PCI target interface. O Copy of the STOPN signal as driven by the PCI target interface. O Inverted copy of the DEVSELN signal as driven by the PCI target interface. O Last transfer in a PCI transaction is occurring. I I Used to delay (add wait states to) a PCI transaction when the back end needs additional time. Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock.
Cfg_MstPERR_Det Usr_TRDYN Usr_STOPN Usr_Devsel Usr_Last_Cycle_D1 Usr_Rdy Usr_Stop
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QL5022 QuickPCI Data Sheet Rev. C
PCI Internal Signals
Table 3: PCI Internal Signals Signal PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 I/O O PCI clock. O PCI reset signal. O Copy of the IRDYN signal from the PCI bus, delayed by one clock. O Copy of the FRAMEN signal from the PCI bus, delayed by one clock. O Copy of the DEVSELN signal from the PCI bus, delayed by one clock. O Copy of the TRDYN signal from the PCI bus, delayed by one clock. O Copy of the STOPN signal from the PCI bus, delayed by one clock. O Copy of the IDSEL signal from the PCI bus, delayed by one clock. Description
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5022 device. Six pins are dedicated to JTAG and programming functions on each QL5022 device, and are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM, is used only for programming.
Development Tool Support
Software support for the QL5022 device is available through the QuickWorks development package. This turnkey PC-based QuickWorks package, shown in Figure 3, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL, Verilog(R), schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify Lite tool, specially tuned to take advantage of the QL5022 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickTools and PC-based QuickWorks and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools and QuickWorks read EDIF netlists and provide support for all QuickLogic devices. QuickTools and QuickWorks also support a wide range of third-party modeling and simulation tools.
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QL5022 QuickPCI Data Sheet Rev. C
QuickWorksDesign Software
Third Party Design Entry & Synthesis SCS Tools Mixed-Mode Design
Schematic Verilog
VHDL/
Turbo HDL Editor
Synplify-Lite HDL Synthesis Simulator Third Party Simulation Optimize, Place, Route Silos III Aldec
Figure 3: QuickWorks Tool Suite
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QL5022 QuickPCI Data Sheet Rev. C
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 10 by the numbers provided in Table 4 through Table 8.
Table 4: Logic Cells Propagation Delays (ns) Fanouta Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 Combinatorial Delay b Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b
2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8
3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8
4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8
8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 10. b. These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5022 QuickPCI Data Sheet Rev. C
Table 5: Input-Only/Clock Cells Propagation Delays (ns) Fanout a Symbol tIN tINI tISU tIH tlCLK tlRST tlESU tlEH Parameter 1 High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 10. Table 6: Clock Cells Propagation Delays (ns) Loads per Half Column a Symbol tACK tGCKP tGCKB Parameter 1 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 11 1.7 0.7 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column.
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QL5022 QuickPCI Data Sheet Rev. C
Table 7: Input-Only I/O Cells Propagation Delays (ns) Fanout a Symbol tI/O tISU tIH tlOCLK tlORST tlESU tlEH Parameter 1 Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 10.
Table 8: Output-Only I/O Cells Propagation Delays (ns) Output Load Capacitance (pF) 30 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State
a
Symbol
Parameter
50 2.5 2.6 1.7 2.0 -
75 3.1 3.2 2.2 2.6 -
100 3.6 3.7 2.8 3.1 -
150 4.7 4.8 3.9 4.2 -
2.1 2.2 1.2 1.6 2.0 1.2
a. The following loads presented in Figure 4 are used for tPXZ:
tPHZ 1 5 pF
1 tPLZ 5 pF
Figure 4: Loads used for tPXZ
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QL5022 QuickPCI Data Sheet Rev. C
DC Characteristics
The DC specifications are provided in Table 9 through Table 11.
Table 9: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to +150C 300C
Table 10: Operating Range Symbol Parameter Industrial Min VCC VCCIO TA TC K Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature Delay Factor -33B Speed Grade 3.0 3.0 -40 0.43 Max 3.6 5.5 85 125 0.9 Commercial Min 3.0 3.0 0 0.46 Max 3.6 5.25 70 0.88 V V C C n/a Unit
Table 11: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mA IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5 VCC -0.5 2.4 0.9 VCC 0.45 0.1 VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO + 0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A
VOL II IOZ CI IOS ICC ICCIO
Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance
a
Output Short Circuit Currentb D.C. Supply Current
c
D.C. Supply Current on VCCIO
a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -33B commercial grade devices only. Maximum Icc is 3 mA for industrial grade devices.
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QL5022 QuickPCI Data Sheet Rev. C
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
Kv
1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Figure 5: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
Kt
Junction Temperature C
Figure 6: Temperature Factor vs. Operating Temperature
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QL5022 QuickPCI Data Sheet Rev. C
QL5022 External Device Pins
The definitions for the QL5022 pin types are listed in Table 12.The names of all QL5022 device pins are indicated in Table 13 and Table 14. These are pins on the device, some of which connect to the PCI bus, and others that are programmable as user I/O.
Table 12: QL5022 External Device Pins Type IN Input. A standard input-only signal Description
OUT Totem pole output. A standard active output driver T/S Tri-state. A bi-directional, tri-state input/output pin
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven S/T/ high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the S PCI system central resource to sustain the inactive state once the active driver has released the signal. O/D Open Drain. Allows multiple devices to share this pin as a wired-or.
Table 13: QL5022 External Device Pins Pin/Bus Name VCC VCCIO GND I I/O GLCK/I ACLK/I TDI/RSI* TDO/RCO* TCK TMS TRSTB/RRO* STM Type IN IN IN IN T/S IN IN IN OUT IN IN IN IN Supply pin. Tie to 3.3 V supply. Supply pin for I/O. Set to 3.3 V for 3.3 V I/O, 5 V for 5.0 V compliant I/O Ground pin. Tie to GND on the PCB. High-drive input. Use for input signals with high fanout. Programmable Input/Output/Tri-State/Bi-directional Pin. Programmable Global Network or Input-only pin. Tie to VCC or GND if unused. Programmable Array Network or Input-only pin. Tie to VCC or GND if unused. JTAG Data In/Ram Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data for RAM init. JTAG Data Out/Ram Init Clock. Leave unconnected if unused. Connect to Serial EPROM clock for RAM init. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for RAM init. QuickLogic Reserved pin. Tie to GND on the PCB. Function
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QL5022 QuickPCI Data Sheet Rev. C
Table 14: QL5022 External Device Pins Pin/Bus Name AD[31:0] CBEN[3:0] Type T/S T/S Function PCI Address and Data 32 bit multiplexed address/data bus. PCI Bus Command and Byte Enables Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. Master drives PAR on address cycles and PCI writes. The Target drives PAR on PCI reads. PCI Cycle Frame Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction.
PAR
T/S
FRAMEN DEVSELN CLK RSTN REQN
S/T/S
S/T/S PCI Device Select Driven by a Target that has decoded a valid base address. IN IN T/S PCI System Clock Input PCI System Reset Input PCI Request Indicates to the Arbiter that this PCI Agent (Initiator) wants to use the bus. A point-to-point signal between the PCI device and the system Arbiter. PCI Grant Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI bus by the Arbiter. A point-to-point signal between the PCI device and the system Arbiter. PCI Data Parity Error Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BEN busses. PCI System Error Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select Use to select a specific PCI Agent during System Initialization.
GNTN
IN
PERRN SERRN IDSEL
S/T/S O/D IN
IRDYN
PCI Initiator Ready Indicates the Initiator's ability to complete a read or write S/T/S transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready Indicates the Target's ability to complete a read or write S/T/S transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. S/T/S PCI Stop Used by a PCI Target to end a burst transaction.
TRDYN STOPN
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QL5022 QuickPCI Data Sheet Rev. C
144 TQFP Pinout Diagram
PIN #109 PIN #1
QuickPCI QL5022-33BPF144C
PIN #37 Figure 7: 144 TQFP Pinout Diagram
PIN #73
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QL5022 QuickPCI Data Sheet Rev. C
144 TQFP Pinout Table
Table 15: 144 TQFP Pinout Table
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function
I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND GNTN I ACLK/I VCC RSTN CLK VCC REQN AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] GND AD[25] AD[24] CBEN[3] IDSEL AD[23] AD[22]
Pin
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Function
AD[21] TDI/RSI AD[20] AD[19] AD[18] VCC AD[17] AD[16] CBEN[2] FRAMEN IRDYN TRDYN DEVSELN GND STOPN PERRN SERRN GND PAR CBEN[1] AD[15] VCCIO AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] TRSTB/RRO TMS
Pin
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Function
AD[4] AD[3] AD[2] AD[1] AD[0] I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
Pin
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Function
TCK STM I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO/RCO I/O
Summary: 49 PCI pins, 63 user I/O, 3 CLK/I, and 3 I.
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(c) 2003 QuickLogic Corporation
QL5022 QuickPCI Data Sheet Rev. C
208 PQFP Pinout Diagram
PIN #157 PIN #1
QuickPCI QL5022-33BPQ208C
PIN #53 Figure 8: 208 PQFP Pinout Diagram
PIN #105
(c) 2003 QuickLogic Corporation
www.quicklogic.com * *
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19
QL5022 QuickPCI Data Sheet Rev. C
208 PQFP Pinout Diagram
Table 16: 208 PQFP Pin Table
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O RSTN ACLK/I VCC I CLK VCC GNTN REQN AD[31] AD[30] AD[29] AD[28]
Pin
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Function
AD[27] AD[26] AD[25] AD[24] VCC CBEN[3] GND IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] CBEN[2] TDI FRAMEN IRDYN TRDYN DEVSELN GND STOPN VCC I/O I/O PERRN I/O SERRN PAR CBEN[1] AD[15] AD[14] AD[13] AD[12]
Pin
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Function
GND AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] VCCIO AD[4] AD[3] AD[2] AD[1] AD[0] I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O
Pin
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Function
I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Function
VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O
Pin
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Function
I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
Summary: 49 PCI pins, 119 user I/O, 3 CLK/I, and 3 I.
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(c) 2003 QuickLogic Corporation
QL5022 QuickPCI Data Sheet Rev. C
Ordering Information
QL 5022 -33B PF144 C QuickLogic Device Operating Range C = Commercial I = Industrial Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP
QuickPCI Device Part Number Speed Grade 33B = 33 MHz standard PCI
Revision History
Revision A B Date November 2002 March 2003 Comments Preliminary release Bernhard Andretzky, Claire Tu, Kathleen Murchek
C
Bernhard Andretzky, David Hrabal and Kathleen Murchkek Udated chip speed grade and operating range in ordering information Updated Figure 1. QL5022 Block Diagram, Table 10. Operating Range September 2003 and Table 11. DC Characteristics. Deleted QuickWorks-Lite information in Development Tool Support section. Added summaries to pinout tables. Added speed grade to Ordering Information section. Updated contact and trademark information.
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 2890 3029 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
(c) 2003 QuickLogic Corporation
www.quicklogic.com * *
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QL5022 QuickPCI Data Sheet Rev. C
Copyright and Trademark Information
Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickDR, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
22 * www.quicklogic.com *
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(c) 2003 QuickLogic Corporation

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